Research shelf / Computer architecture / CPU
Written Updated
What if fork, syscalls and page faults were RTL?
Most open CPU-design material is either a teaching core in a few hundred lines of Verilog or a vendor architecture PDF. This folder is the awkward middle: a design conversation establishing targets for a 16-big-core, 4,096-small-core machine, paired with RTL that accelerates the things operating systems usually do entirely in software.
Theory or design only. No in-house measurement.
A heterogeneous many-core architecture discussion paired with a SystemVerilog sketch that moves operating-system primitives — context switch, syscall dispatch, page-fault handling — into hardware.
The architecture side sets targets rather than specifications: 16 large out-of-order cores at 4 GHz on 8-stage pipelines alongside 4,096 small cores, a four-level cache hierarchy ending in 4 GiB of shared L4, MOESI coherence, DDR5 at 7,800 MT/s, hardware-accelerated virtualisation, and a Power-ISA-inspired (explicitly not clone) instruction encoding.
The HDL side is an os_accelerator block containing three sub-accelerators — syscall dispatch with a four-argument bundle, context switching over 32 × 64-bit registers plus PC, SP and flags, and memory management handling PAGE_FAULT, TLB_MISS and MEMORY_MAP cases — parameterised at a 1,024-entry process table and 512-byte context. Inside it, a hardware_bios state machine walks POWER_ON_SELF_TEST → HARDWARE_INIT → MEMORY_TEST → BOOT_SEQUENCE → SYSTEM_INIT → OS_HANDOFF.
The folder is explicit that this is not a buildable CPU. The nested-module HDL pattern is not synthesisable as written and would need restructuring; the architecture material is a transcript rather than a specification. It reads best as architecture-fiction with HDL scaffolding — the artefact that comes before anyone builds anything.
Every number, and what stands behind it
A claim is only worth the evidence attached to it. Each row below carries its basis: measured on the author’s own hardware, derived from the construction, measured on synthetic data, projected from literature, or simply cited.
| Claim | Figure | Basis | Context |
|---|---|---|---|
| Big cores | 16 × 4 GHz, 8-stage OOO | Projected | Design target from the conversation log |
| Small cores | 4,096 | Projected | Heterogeneous big.LITTLE-style |
| Cache hierarchy | L1 64 KiB / L2 512 KiB / L3 4 MiB / L4 4 GiB shared | Projected | Four levels |
| Coherence protocol | MOESI | Derived | Design choice |
| Memory | DDR5 7,800 MT/s | Projected | Target |
| Process table size | 1,024 entries | Derived | os_accelerator parameter |
| Context size | 512 bytes (32 × 64-bit + PC/SP/flags) | Derived | context_t definition |
| BIOS state machine | 6 states | Derived | POWER_ON_SELF_TEST through OS_HANDOFF |
| Synthesisability | not synthesisable as written | Derived | Nested module pattern — the folder says so |
Measured — author-run experiment on the stated setup. Synthetic — measured, but on synthetic rather than real data. Derived — follows from the stated construction or proof. Projected — paper-stated projection, not an author-run benchmark. Cited — taken from external literature.
How it works
- Hardware syscall dispatch. Four-argument syscall bundle dispatched by dedicated RTL rather than a software trap handler.
- Hardware context switch. Full architectural state — 32 registers plus PC, SP and flags — swapped by a dedicated block.
- Hardware memory management. PAGE_FAULT, TLB_MISS and MEMORY_MAP as RTL cases rather than kernel code paths.
- Hardware BIOS state machine. The boot sequence as a six-state FSM inside the accelerator.
What it does not do
Taken from the folder’s own README. Nothing here has been softened.
- Not a buildable CPU. The folder states this directly.
- The HDL uses nested modules, which is not synthesisable and would require restructuring before any tooling accepts it.
- The architecture material is a conversation transcript, not a specification: no ISA encoding, no pipeline diagram, no verification plan.
- No simulation, no synthesis, no performance model — every architectural number is a target.
- Putting OS primitives in RTL raises security and flexibility questions (privilege, updatability) that are not addressed.
Free under AGPL-3.0+ for almost everyone
Personal use, charities, education and organisations under AUD 50,000 a year pay nothing. A tiered commercial licence covers everyone else.